patch-2.4.21 linux-2.4.21/arch/ppc/kernel/ppc8xx_pic.c
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- Lines: 144
- Date:
2003-06-13 07:51:31.000000000 -0700
- Orig file:
linux-2.4.20/arch/ppc/kernel/ppc8xx_pic.c
- Orig date:
2002-02-25 11:37:55.000000000 -0800
diff -urN linux-2.4.20/arch/ppc/kernel/ppc8xx_pic.c linux-2.4.21/arch/ppc/kernel/ppc8xx_pic.c
@@ -1,6 +1,3 @@
-/*
- * BK Id: SCCS/s.ppc8xx_pic.c 1.13 12/01/01 17:19:48 trini
- */
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/init.h>
@@ -11,6 +8,8 @@
#include <asm/mpc8xx.h>
#include "ppc8xx_pic.h"
+extern int cpm_get_irq(struct pt_regs *regs);
+
/* The 8xx internal interrupt controller. It is usually
* the only interrupt controller. Some boards, like the MBX and
* Sandpoint have the 8259 as a secondary controller. Depending
@@ -83,36 +82,6 @@
0
};
-#if 0
-void
-m8xx_do_IRQ(struct pt_regs *regs,
- int cpu)
-{
- int irq;
- unsigned long bits = 0;
-
- /* For MPC8xx, read the SIVEC register and shift the bits down
- * to get the irq number. */
- bits = ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec;
- irq = bits >> 26;
-#if 0
- irq += ppc8xx_pic.irq_offset;
-#endif
- bits = 1UL << irq;
-
- if (irq < 0) {
- printk(KERN_DEBUG "Bogus interrupt %d from PC = %lx\n",
- irq, regs->nip);
- ppc_spurious_interrupts++;
- }
- else {
- ppc_irq_dispatch_handler( regs, irq );
- }
-
-}
-#endif
-
-
/*
* We either return a valid interrupt or -1 if there is nothing pending
*/
@@ -130,70 +99,31 @@
* When we read the sivec without an interrupt to process, we will
* get back SIU_LEVEL7. In this case, return -1
*/
- if (irq == SIU_LEVEL7)
- return -1;
+ if (irq == CPM_INTERRUPT)
+ irq = CPM_IRQ_OFFSET + cpm_get_irq(regs);
+#if defined(CONFIG_PCI)
+ else if (irq == ISA_BRIDGE_INT) {
+ int isa_irq;
+
+ if ((isa_irq = i8259_poll(regs)) >= 0)
+ irq = I8259_IRQ_OFFSET + isa_irq;
+ }
+#endif /* CONFIG_PCI */
+ else if (irq == SIU_LEVEL7)
+ irq = -1;
return irq;
}
-/* The MBX is the only 8xx board that uses the 8259.
-*/
-#if defined(CONFIG_MBX) && defined(CONFIG_PCI)
-void mbx_i8259_action(int cpl, void *dev_id, struct pt_regs *regs)
-{
- int bits, irq;
-
- /* A bug in the QSpan chip causes it to give us 0xff always
- * when doing a character read. So read 32 bits and shift.
- * This doesn't seem to return useful values anyway, but
- * read it to make sure things are acked.
- * -- Cort
- */
- irq = (inl(0x508) >> 24)&0xff;
- if ( irq != 0xff ) printk("iack %d\n", irq);
-
- outb(0x0C, 0x20);
- irq = inb(0x20) & 7;
- if (irq == 2)
- {
- outb(0x0C, 0xA0);
- irq = inb(0xA0);
- irq = (irq&7) + 8;
- }
- bits = 1UL << irq;
- irq += i8259_pic.irq_offset;
- ppc_irq_dispatch_handler( regs, irq );
-}
-#endif
-
-/* Only the MBX uses the external 8259. This allows us to catch standard
- * drivers that may mess up the internal interrupt controllers, and also
- * allow them to run without modification on the MBX.
+#if defined(CONFIG_PCI)
+/* Handler for the MPC8xx SIU cascade interrupt for the 8259 interrupt
+ * controller
*/
-int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *),
- unsigned long irqflags, const char * devname, void *dev_id)
+void mbx_i8259_action(int irq, void *dev_id, struct pt_regs *regs)
{
-
-#if defined(CONFIG_MBX) && defined(CONFIG_PCI)
- irq += i8259_pic.irq_offset;
- return (request_8xxirq(irq, handler, irqflags, devname, dev_id));
-#else
- /*
- * Handle other "well-known" interrupts, but panic on unknown ones.
+ /* This interrupt handler never actually gets called. It is
+ * installed only to unmask the 8259 cascade interrupt in the SIU
+ * and to make the 8259 cascade interrupt visible in /proc/interrupts.
*/
- switch (irq) {
-#ifdef IDE0_INTERRUPT
- case IDE0_INTERRUPT: /* IDE0 */
- return (request_8xxirq(irq, handler, irqflags, devname,
- dev_id));
-#endif
-#ifdef IDE1_INTERRUPT
- case IDE1_INTERRUPT: /* IDE1 */
- return (request_8xxirq(irq, handler, irqflags, devname,
- dev_id));
-#endif
- default: /* unknown IRQ -> panic */
- panic("request_irq");
- }
-#endif
}
+#endif /* CONFIG_PCI */
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