patch-2.4.25 linux-2.4.25/include/asm-mips/serial.h

• Lines: 155
• Date: 2004-02-18 05:36:32.000000000 -0800
• Orig file: linux-2.4.24/include/asm-mips/serial.h
• Orig date: 2003-08-25 04:44:44.000000000 -0700

diff -urN linux-2.4.24/include/asm-mips/serial.h linux-2.4.25/include/asm-mips/serial.h
@@ -6,6 +6,9 @@
  * Copyright (C) 1999 by Ralf Baechle
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
+#ifndef _ASM_SERIAL_H
+#define _ASM_SERIAL_H
+
 #include <linux/config.h>
 #include <asm/jazz.h>
 
@@ -269,8 +272,8 @@
 #define OCELOT_SERIAL1_BASE	0xe0001020
 
 #define _OCELOT_SERIAL_INIT(int, base)					\
-	{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,	\
-	  .iomem_base = (u8 *) base, .iomem_reg_shift = 2,			\
+	{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
+	  .iomem_base = (u8 *) base, .iomem_reg_shift = 2,		\
 	  .io_type = SERIAL_IO_MEM }
 #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS				\
 	_OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
@@ -291,7 +294,7 @@
 
 #define _OCELOT_G_SERIAL_INIT(int, base)				\
 	{ .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
-	  .iomem_base = (u8 *) base, .iomem_reg_shift = 2,			\
+	  .iomem_base = (u8 *) base, .iomem_reg_shift = 2,		\
 	  .io_type = SERIAL_IO_MEM }
 #define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS				\
 	_OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
@@ -320,33 +323,111 @@
 #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
 #endif
 
+#ifdef CONFIG_MOMENCO_JAGUAR_ATX
+/* Ordinary NS16552 duart with a 20MHz crystal.  */
+#define JAGUAR_ATX_BASE_BAUD ( 20000000 / 16 )
+
+#define JAGUAR_ATX_SERIAL1_IRQ	7
+#define JAGUAR_ATX_SERIAL1_BASE	0xfffffffffd000020
+
+#define _JAGUAR_ATX_SERIAL_INIT(int, base)				\
+	{ baud_base: JAGUAR_ATX_BASE_BAUD, irq: int,			\
+	  flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),		\
+	  iomem_base: (u8 *) base, iomem_reg_shift: 2,			\
+	  io_type: SERIAL_IO_MEM }
+#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS				\
+	_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
+#else
+#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_TITAN_SERIAL
+/* 16552 20 MHz crystal */
+#define TITAN_SERIAL_BASE_BAUD	( 20000000 / 16 )
+#define	TITAN_SERIAL_IRQ	XXX
+#define	TITAN_SERIAL_BASE	0xffffffff
+
+#define	_TITAN_SERIAL_INIT(int, base)					\
+	{ baud_base: TITAN_SERIAL_BASE_BAUD, irq: int,			\
+	  flags: STD_COM_FLAGS,	iomem_base: (u8 *) base,		\
+	  iomem_reg_shift: 2, io_type: SERIAL_IO_MEM			\
+	}
+
+#define TITAN_SERIAL_PORT_DEFNS						\
+	_TITAN_SERIAL_INIT(TITAN_SERIAL_IRQ, TITAN_SERIAL_BASE)
+#else
+#define TITAN_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_SGI_IP27
+
+/*
+ * Note about serial ports and consoles:
+ * For console output, everyone uses the IOC3 UARTA (offset 0x178)
+ * connected to the master node (look in ip27_setup_console() and
+ * ip27prom_console_write()).
+ *
+ * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
+ * addresses on a partitioned machine. Since we currently use the ioc3
+ * serial ports, we use dynamic serial port discovery that the serial.c
+ * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
+ * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
+ * than UARTB's, although UARTA on o200s has traditionally been known as
+ * port 0. So, we just use one serial port from each ioc3 (since the
+ * serial driver adds addresses to get to higher ports).
+ *
+ * The first one to do a register_console becomes the preferred console
+ * (if there is no kernel command line console= directive). /dev/console
+ * (ie 5, 1) is then "aliased" into the device number returned by the
+ * "device" routine referred to in this console structure
+ * (ip27prom_console_dev).
+ *
+ * Also look in ip27-pci.c:pci_fixuop_ioc3() for some comments on working
+ * around ioc3 oddities in this respect.
+ *
+ * The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
+ * (IOC3_BAUD = (22000000 / (3*16)))
+ *
+ * At the moment this is only a skeleton definition as we register all serials
+ * at runtime.
+ */
+
+#define IP27_SERIAL_PORT_DEFNS
+#else
+#define IP27_SERIAL_PORT_DEFNS
+#endif /* CONFIG_SGI_IP27 */
+
 #ifdef CONFIG_DDB5477
 #include <asm/ddb5xxx/ddb5477.h>
-#define DDB5477_SERIAL_PORT_DEFNS                                       \
-        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, 		\
-	  .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, 	\
+#define DDB5477_SERIAL_PORT_DEFNS					 \
+	{  .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0,		\
+	  .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200,	\
 	  .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},		\
-        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, 		\
-	  .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, 	\
+	{  .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1,		\
+	  .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240,	\
 	  .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
 #else
 #define DDB5477_SERIAL_PORT_DEFNS
 #endif
 
 #define SERIAL_PORT_DFNS			\
-	IVR_SERIAL_PORT_DEFNS           	\
-	ITE_SERIAL_PORT_DEFNS           	\
 	ATLAS_SERIAL_PORT_DEFNS			\
-	SEAD_SERIAL_PORT_DEFNS			\
+	AU1000_SERIAL_PORT_DEFNS		\
 	COBALT_SERIAL_PORT_DEFNS		\
+	DDB5477_SERIAL_PORT_DEFNS		\
 	EV96100_SERIAL_PORT_DEFNS		\
-	JAZZ_SERIAL_PORT_DEFNS			\
-	STD_SERIAL_PORT_DEFNS			\
 	EXTRA_SERIAL_PORT_DEFNS			\
 	HUB6_SERIAL_PORT_DFNS			\
+	ITE_SERIAL_PORT_DEFNS           	\
+	IVR_SERIAL_PORT_DEFNS           	\
+	JAZZ_SERIAL_PORT_DEFNS			\
 	MOMENCO_OCELOT_SERIAL_PORT_DEFNS	\
 	MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS	\
 	MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS	\
-	AU1000_SERIAL_PORT_DEFNS		\
-	TXX927_SERIAL_PORT_DEFNS        	\
-	DDB5477_SERIAL_PORT_DEFNS
+	MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS	\
+	SEAD_SERIAL_PORT_DEFNS			\
+	STD_SERIAL_PORT_DEFNS			\
+	TITAN_SERIAL_PORT_DEFNS			\
+	TXX927_SERIAL_PORT_DEFNS
+
+#endif /* _ASM_SERIAL_H */