patch-2.4.19 linux-2.4.19/include/asm-mips64/pgtable.h
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- Lines: 737
- Date:
Fri Aug 2 17:39:45 2002
- Orig file:
linux-2.4.18/include/asm-mips64/pgtable.h
- Orig date:
Sun Sep 9 10:43:02 2001
diff -urN linux-2.4.18/include/asm-mips64/pgtable.h linux-2.4.19/include/asm-mips64/pgtable.h
@@ -9,15 +9,16 @@
#ifndef _ASM_PGTABLE_H
#define _ASM_PGTABLE_H
+#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/page.h>
-#ifndef _LANGUAGE_ASSEMBLY
+#ifndef __ASSEMBLY__
#include <linux/linkage.h>
-#include <linux/config.h>
#include <linux/mmzone.h>
#include <asm/cachectl.h>
+#include <asm/io.h>
/* Cache flushing:
*
@@ -27,30 +28,30 @@
* - flush_cache_range(mm, start, end) flushes a range of pages
* - flush_page_to_ram(page) write back kernel page to ram
*/
+extern void (*_flush_cache_all)(void);
+extern void (*___flush_cache_all)(void);
extern void (*_flush_cache_mm)(struct mm_struct *mm);
extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
- unsigned long end);
-extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
+ unsigned long end);
+extern void (*_flush_cache_page)(struct vm_area_struct *vma,
+ unsigned long page);
extern void (*_flush_page_to_ram)(struct page * page);
+extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*_flush_icache_page)(struct vm_area_struct *vma,
+ struct page *page);
+extern void (*_flush_cache_sigtramp)(unsigned long addr);
+extern void (*_flush_icache_all)(void);
-#define flush_cache_all() do { } while(0)
-#define flush_dcache_page(page) do { } while (0)
+/* These suck ... */
+extern void (*_flush_cache_l2)(void);
+extern void (*_flush_cache_l1)(void);
-#ifndef CONFIG_CPU_R10000
-#define flush_cache_mm(mm) _flush_cache_mm(mm)
-#define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end)
-#define flush_cache_page(vma,page) _flush_cache_page(vma, page)
-#define flush_page_to_ram(page) _flush_page_to_ram(page)
-#define flush_icache_range(start, end) _flush_cache_l1()
+#define flush_cache_all() _flush_cache_all()
+#define __flush_cache_all() ___flush_cache_all()
+#define flush_dcache_page(page) do { } while (0)
-#define flush_icache_page(vma, page) \
-do { \
- unsigned long addr; \
- addr = (unsigned long) page_address(page); \
- _flush_cache_page(vma, addr); \
-} while (0)
-#else /* !CONFIG_CPU_R10000 */
+#ifdef CONFIG_CPU_R10000
/*
* Since the r10k handles VCEs in hardware, most of the flush cache
* routines are not needed. Only the icache on a processor is not
@@ -66,22 +67,44 @@
#define flush_cache_page(vma,page) do { } while(0)
#define flush_page_to_ram(page) do { } while(0)
#define flush_icache_range(start, end) _flush_cache_l1()
+#define flush_icache_user_range(vma, page, addr, len) \
+ flush_icache_page((vma), (page))
#define flush_icache_page(vma, page) \
do { \
if ((vma)->vm_flags & VM_EXEC) \
- andes_flush_icache_page(page_address(page)); \
+ andes_flush_icache_page(phys_to_virt(page_to_phys(page))); \
} while (0)
-#endif /* !CONFIG_CPU_R10000 */
-/*
- * The foll cache flushing routines are MIPS specific.
- * flush_cache_l2 is needed only during initialization.
- */
-extern void (*_flush_cache_sigtramp)(unsigned long addr);
-extern void (*_flush_cache_l2)(void);
-extern void (*_flush_cache_l1)(void);
+#else
+
+extern void (*_flush_icache_all)(void);
+extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page);
+
+#define flush_cache_mm(mm) _flush_cache_mm(mm)
+#define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end)
+#define flush_cache_page(vma,page) _flush_cache_page(vma, page)
+#define flush_page_to_ram(page) _flush_page_to_ram(page)
+#define flush_icache_range(start, end) _flush_icache_range(start, end)
+#define flush_icache_user_range(vma, page, addr, len) \
+ flush_icache_page((vma), (page))
+#define flush_icache_page(vma, page) _flush_icache_page(vma, page)
+#ifdef CONFIG_VTAG_ICACHE
+#define flush_icache_all() _flush_icache_all()
+#else
+#define flush_icache_all() do { } while(0)
+#endif
+
+
+#endif /* !CONFIG_CPU_R10000 */
#define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr)
+#ifdef CONFIG_VTAG_ICACHE
+#define flush_icache_all() _flush_icache_all()
+#else
+#define flush_icache_all() do { } while(0)
+#endif
+
#define flush_cache_l2() _flush_cache_l2()
#define flush_cache_l1() _flush_cache_l1()
@@ -105,7 +128,7 @@
* vmalloc range translations, which the fault handler looks at.
*/
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+#endif /* !__ASSEMBLY__ */
/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3))
@@ -129,7 +152,7 @@
#define VMALLOC_START XKSEG
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END \
- (VMALLOC_START + ((1 << KPTBL_PAGE_ORDER) * PTRS_PER_PTE * PAGE_SIZE))
+ (VMALLOC_START + ((1 << KPTBL_PAGE_ORDER) * PTRS_PER_PTE * PAGE_SIZE))
/* Note that we shift the lower 32bits of each EntryLo[01] entry
* 6 bits to the left. That way we can convert the PFN into the
@@ -169,7 +192,7 @@
#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00 only */
#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */
#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */
-#define _CACHE_CACHABLE_ACCELERATED (7<<9) /* R10000 only */
+#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */
#define _CACHE_MASK (7<<9)
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
@@ -195,11 +218,11 @@
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
PAGE_CACHABLE_DEFAULT)
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
- PAGE_CACHABLE_DEFAULT)
+ _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
_CACHE_UNCACHED)
-#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
- _CACHE_UNCACHED)
+#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
+ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
/*
* MIPS can't do page protection for execute, and considers that the same like
@@ -224,7 +247,7 @@
#define __S110 PAGE_SHARED
#define __S111 PAGE_SHARED
-#if !defined (_LANGUAGE_ASSEMBLY)
+#ifndef __ASSEMBLY__
#define pte_ERROR(e) \
printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
@@ -244,21 +267,6 @@
#define ZERO_PAGE(vaddr) \
(virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
-/* number of bits that fit into a memory pointer */
-#define BITS_PER_PTR (8*sizeof(unsigned long))
-
-/* to align the pointer to a pointer address */
-#define PTR_MASK (~(sizeof(void*)-1))
-
-/*
- * sizeof(void*) == (1 << SIZEOF_PTR_LOG2)
- */
-#define SIZEOF_PTR_LOG2 3
-
-/* to find an entry in a page-table */
-#define PAGE_PTR(address) \
-((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
-
extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)];
extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
@@ -268,32 +276,32 @@
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
-extern inline unsigned long pmd_page(pmd_t pmd)
+static inline unsigned long pmd_page(pmd_t pmd)
{
return pmd_val(pmd);
}
-extern inline unsigned long pgd_page(pgd_t pgd)
+static inline unsigned long pgd_page(pgd_t pgd)
{
return pgd_val(pgd);
}
-extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
+static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
{
pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
}
-extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
+static inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
{
pgd_val(*pgdp) = (((unsigned long) pmdp) & PAGE_MASK);
}
-extern inline int pte_none(pte_t pte)
+static inline int pte_none(pte_t pte)
{
return !pte_val(pte);
}
-extern inline int pte_present(pte_t pte)
+static inline int pte_present(pte_t pte)
{
return pte_val(pte) & _PAGE_PRESENT;
}
@@ -303,12 +311,12 @@
* within a page table are directly modified. Thus, the following
* hook is made available.
*/
-extern inline void set_pte(pte_t *ptep, pte_t pteval)
+static inline void set_pte(pte_t *ptep, pte_t pteval)
{
*ptep = pteval;
}
-extern inline void pte_clear(pte_t *ptep)
+static inline void pte_clear(pte_t *ptep)
{
set_pte(ptep, __pte(0));
}
@@ -323,22 +331,22 @@
/*
* Empty pmd entries point to the invalid_pte_table.
*/
-extern inline int pmd_none(pmd_t pmd)
+static inline int pmd_none(pmd_t pmd)
{
return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}
-extern inline int pmd_bad(pmd_t pmd)
+static inline int pmd_bad(pmd_t pmd)
{
return pmd_val(pmd) &~ PAGE_MASK;
}
-extern inline int pmd_present(pmd_t pmd)
+static inline int pmd_present(pmd_t pmd)
{
return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}
-extern inline void pmd_clear(pmd_t *pmdp)
+static inline void pmd_clear(pmd_t *pmdp)
{
pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}
@@ -346,31 +354,26 @@
/*
* Empty pgd entries point to the invalid_pmd_table.
*/
-extern inline int pgd_none(pgd_t pgd)
+static inline int pgd_none(pgd_t pgd)
{
return pgd_val(pgd) == (unsigned long) invalid_pmd_table;
}
-extern inline int pgd_bad(pgd_t pgd)
+static inline int pgd_bad(pgd_t pgd)
{
return pgd_val(pgd) &~ PAGE_MASK;
}
-extern inline int pgd_present(pgd_t pgd)
+static inline int pgd_present(pgd_t pgd)
{
return pgd_val(pgd) != (unsigned long) invalid_pmd_table;
}
-extern inline void pgd_clear(pgd_t *pgdp)
+static inline void pgd_clear(pgd_t *pgdp)
{
pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table);
}
-/*
- * Permanent address of a page. On MIPS64 we never have highmem, so this
- * is simple.
- */
-#define page_address(page) ((page)->virtual)
#ifndef CONFIG_DISCONTIGMEM
#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT)))
#else
@@ -384,51 +387,51 @@
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
-extern inline int pte_read(pte_t pte)
+static inline int pte_read(pte_t pte)
{
return pte_val(pte) & _PAGE_READ;
}
-extern inline int pte_write(pte_t pte)
+static inline int pte_write(pte_t pte)
{
return pte_val(pte) & _PAGE_WRITE;
}
-extern inline int pte_dirty(pte_t pte)
+static inline int pte_dirty(pte_t pte)
{
return pte_val(pte) & _PAGE_MODIFIED;
}
-extern inline int pte_young(pte_t pte)
+static inline int pte_young(pte_t pte)
{
return pte_val(pte) & _PAGE_ACCESSED;
}
-extern inline pte_t pte_wrprotect(pte_t pte)
+static inline pte_t pte_wrprotect(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
return pte;
}
-extern inline pte_t pte_rdprotect(pte_t pte)
+static inline pte_t pte_rdprotect(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
return pte;
}
-extern inline pte_t pte_mkclean(pte_t pte)
+static inline pte_t pte_mkclean(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
return pte;
}
-extern inline pte_t pte_mkold(pte_t pte)
+static inline pte_t pte_mkold(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
return pte;
}
-extern inline pte_t pte_mkwrite(pte_t pte)
+static inline pte_t pte_mkwrite(pte_t pte)
{
pte_val(pte) |= _PAGE_WRITE;
if (pte_val(pte) & _PAGE_MODIFIED)
@@ -436,7 +439,7 @@
return pte;
}
-extern inline pte_t pte_mkread(pte_t pte)
+static inline pte_t pte_mkread(pte_t pte)
{
pte_val(pte) |= _PAGE_READ;
if (pte_val(pte) & _PAGE_ACCESSED)
@@ -444,7 +447,7 @@
return pte;
}
-extern inline pte_t pte_mkdirty(pte_t pte)
+static inline pte_t pte_mkdirty(pte_t pte)
{
pte_val(pte) |= _PAGE_MODIFIED;
if (pte_val(pte) & _PAGE_WRITE)
@@ -452,7 +455,7 @@
return pte;
}
-extern inline pte_t pte_mkyoung(pte_t pte)
+static inline pte_t pte_mkyoung(pte_t pte)
{
pte_val(pte) |= _PAGE_ACCESSED;
if (pte_val(pte) & _PAGE_READ)
@@ -485,8 +488,8 @@
#define PAGE_TO_PA(page) ((page - mem_map) << PAGE_SHIFT)
#else
#define PAGE_TO_PA(page) \
- ((((page)-(page)->zone->zone_mem_map) << PAGE_SHIFT) \
- + ((page)->zone->zone_start_paddr))
+ ((((page) - page_zone(page)->zone_mem_map) << PAGE_SHIFT) \
+ + (page_zone(page)->zone_start_paddr))
#endif
#define mk_pte(page, pgprot) \
({ \
@@ -498,12 +501,12 @@
__pte; \
})
-extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
+static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
{
return __pte(physpage | pgprot_val(pgprot));
}
-extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
}
@@ -516,20 +519,20 @@
#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
/* to find an entry in a page-table-directory */
-extern inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
+static inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
{
return mm->pgd + pgd_index(address);
}
/* Find an entry in the second-level page table.. */
-extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
+static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
{
return (pmd_t *) pgd_page(*dir) +
((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
}
/* Find an entry in the third-level page table.. */
-extern inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
+static inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
{
return (pte_t *) (pmd_page(*dir)) +
((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
@@ -544,14 +547,15 @@
extern pgd_t swapper_pg_dir[1024];
extern void paging_init(void);
-extern void (*update_mmu_cache)(struct vm_area_struct *vma,
- unsigned long address, pte_t pte);
+extern void (*_update_mmu_cache)(struct vm_area_struct *vma,
+ unsigned long address, pte_t pte);
+#define update_mmu_cache(vma, address, pte) _update_mmu_cache(vma, address, pte)
/*
* Non-present pages: high 24 bits are offset, next 8 bits type,
* low 32 bits zero.
*/
-extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
+static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
#define SWP_TYPE(x) (((x).val >> 32) & 0xff)
@@ -566,259 +570,19 @@
#define kern_addr_valid(addr) (1)
#endif
-/* TLB operations. */
-extern inline void tlb_probe(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbp\n\t"
- ".set reorder");
-}
-
-extern inline void tlb_read(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbr\n\t"
- ".set reorder");
-}
-
-extern inline void tlb_write_indexed(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbwi\n\t"
- ".set reorder");
-}
-
-extern inline void tlb_write_random(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbwr\n\t"
- ".set reorder");
-}
-
-/* Dealing with various CP0 mmu/cache related registers. */
-
-/* CP0_PAGEMASK register */
-extern inline unsigned long get_pagemask(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $5\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_pagemask(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $5\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
-extern inline unsigned long get_entrylo0(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $2\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_entrylo0(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $2\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_entrylo1(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $3\n\t"
- ".set reorder" : "=r" (val));
-
- return val;
-}
-
-extern inline void set_entrylo1(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $3\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYHI register */
-extern inline unsigned long get_entryhi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $10\n\t"
- ".set reorder"
- : "=r" (val));
-
- return val;
-}
-
-extern inline void set_entryhi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $10\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_INDEX register */
-extern inline unsigned int get_index(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $0\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_index(unsigned int val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $0\n\t"
- ".set reorder\n\t"
- : : "Jr" (val));
-}
-
-/* CP0_WIRED register */
-extern inline unsigned long get_wired(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $6\n\t"
- ".set reorder\n\t"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_wired(unsigned long val)
-{
- __asm__ __volatile__(
- "\n\t.set noreorder\n\t"
- "mtc0 %z0, $6\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_info(void)
-{
- unsigned long val;
-
- __asm__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $7\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-/* CP0_TAGLO and CP0_TAGHI registers */
-extern inline unsigned long get_taglo(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $28\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_taglo(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $28\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_taghi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $29\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_taghi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $29\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_CONTEXT register */
-extern inline unsigned long get_context(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $4\n\t"
- ".set reorder"
- : "=r" (val));
-
- return val;
-}
-
-extern inline void set_context(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $4\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init() do { } while (0)
#include <asm-generic/pgtable.h>
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
/*
- * No page table caches to initialise
+ * We provide our own get_unmapped area to cope with the virtual aliasing
+ * constraints placed on us by the cache architecture.
*/
-#define pgtable_cache_init() do { } while (0)
+#define HAVE_ARCH_UNMAPPED_AREA
+
+#endif /* !__ASSEMBLY__ */
#endif /* _ASM_PGTABLE_H */
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)