patch-2.4.13 linux/arch/i386/kernel/mtrr.c

• Lines: 36
• Date: Mon Oct 15 13:43:24 2001
• Orig file: v2.4.12/linux/arch/i386/kernel/mtrr.c
• Orig date: Sun Sep 23 11:40:55 2001

diff -u --recursive --new-file v2.4.12/linux/arch/i386/kernel/mtrr.c linux/arch/i386/kernel/mtrr.c
@@ -1253,7 +1253,8 @@
 	break;
 
     case MTRR_IF_INTEL:
-	/*  For Intel PPro stepping <= 7, must be 4 MiB aligned  */
+	/*  For Intel PPro stepping <= 7, must be 4 MiB aligned 
+	    and not touch 0x70000000->0x7003FFFF */
 	if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 	     boot_cpu_data.x86 == 6 &&
 	     boot_cpu_data.x86_model == 1 &&
@@ -1264,6 +1265,12 @@
 		printk (KERN_WARNING "mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
 		return -EINVAL;
 	    }
+	    if (!(base + size < 0x70000000 || base > 0x7003FFFF) &&
+		 (type == MTRR_TYPE_WRCOMB || type == MTRR_TYPE_WRBACK))
+	    {
+		printk (KERN_WARNING "mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
+	        return -EINVAL;
+	    }
 	}
 	/* Fall through */
 	
@@ -2119,10 +2126,8 @@
 		break;
 
 	case X86_VENDOR_CENTAUR:
-		/* Cyrix III has Intel style MTRRs, but doesn't support PAE */
-		if (boot_cpu_data.x86 == 6 &&
-			(boot_cpu_data.x86_model == 6 ||
-			 boot_cpu_data.x86_model == 7)) {
+		/* VIA Cyrix family have Intel style MTRRs, but don't support PAE */
+		if (boot_cpu_data.x86 == 6) {
 			size_or_mask  = 0xfff00000; /* 32 bits */
 			size_and_mask = 0;
 		}